In the case of semiconductor memory devices, one differentiates between so-called functional memory devices (e.g. PLAs, PALs, etc.), and so-called table memory devices, e.g. ROM devices (ROM=Read Only Memory) and RAM devices (RAM=Random Access Memory or read-write memory).
A RAM device is a memory for storing data under a predetermined address and for reading out the data under this address later.
The corresponding address may be input into the RAM device via so-called address input pins; for the input and output of the data, a plurality, e.g. 16, so-called data input/output pins (I/Os or Input/Outputs) are provided. By applying an appropriate signal (e.g. a read/write signal) at a write/read selection pin it may be selected whether data are to be stored or to be read out (at the moment).
Since it is intended to accommodate as many memory cells as possible in one RAM device, one has been trying to realize them as simple as possible. In the case of so-called SRAMs (SRAM=Static Random Access Memory), the individual memory cells consist e.g. of few, for instance 6, transistors, and in the case of so-called DRAMs (DRAM=Dynamic Random Access Memory) in general only of one single, correspondingly controlled capacitor with the capacitance of which one bit each can be stored as charge. This charge, however, remains for a short time only. Therefore, a so-called “refresh” must be performed regularly, e.g. approximately every 64 ms.
For technological reasons, the individual memory cells are, in the case of memory devices, in particular DRAM devices, arranged side by side in a plurality of rows and columns in a rectangular matrix or a rectangular array, respectively.
In order to achieve a correspondingly high overall storage capacity and/or a data read or write rate that is as high as possible, a plurality of, e.g. four—substantially rectangular—(sub) arrays may be provided in an individual RAM device or chip (“multi-bank chip”) instead of one single array.
To perform a write or read access, a particular, predetermined sequence of commands has to be run through:
By means of a word line activate command (activate command (ACT)), a corresponding word line—that is, in particular, assigned to a particular subarray (“memory bank”)—(and that is defined by the row address (“row address”)) is, for instance, activated first of all.
Subsequently—by means of a corresponding read or write command (Read (RD) or Write (WT) command)—it is initiated that the corresponding data—that are then exactly specified by the corresponding column address (“column address”)—are correspondingly output (or read in).
Next—by means of a word line deactivate command (e.g. a precharge command (PRE command))—the corresponding word line is deactivated again, and the corresponding subarray (“memory bank”) is prepared for the next word line activate command (activate command (ACT)).
To guarantee a faultless operation of the DRAM device, particular time conditions have to be met.
For instance, a particular time interval tRCD must lie between the word line activate command (ACT command) and a corresponding read (or write) command (RD (or WT) command). This delay results, for instance, from the time required by the sense amplifiers for amplifying the data supplied by the memory cells addressed by the word line.
Similarly, a particular time interval also has to lie e.g. between the read (or write) command (RD (or WT) command) and the outputting (or inputting) of the data at corresponding data pins of the DRAM device (so-called CAS latency or Column Address Strobe latency, respectively).
Furthermore, an appropriate time interval tRP (so-called “row precharge time” delay) must also be kept correspondingly between the read (or write) command (RD (or WT) command) and a subsequent word line deactivate command (PRE command).
The size CL of the respective, above-mentioned CAS latency (Column Address Strobe latency)—or a value CL indicating the number of clocks passing between the read command and the valid data output—may be programmed in a register provided on the DRAM device (wherein there may e.g. apply: CL=2, 3, 4, or 5, etc.).
If, in a corresponding DRAM device, circuits are used that improve the high frequency behavior (e.g. appropriate duty cycle correction circuits (cf. e.g. IEEE Journal of Solid-State Circuits, vol. 36, pages 784-791, May 2001)), the corresponding device may be operated at higher clock frequency than in normal operation (“high performance operation”).
The CL value stored in the above-mentioned CAS latency register is then re-programmed correspondingly (so that a correspondingly different CL value is stored in the CAS latency register in high performance operation than in normal operation).
The use of the above-mentioned duty cycle correction circuit, however, results in a correspondingly high additional electric power consumption caused by the correction circuit. This is not acceptable for many applications.